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stm32 /stm32h7rs /STM32H7R /DBGMCU /DBGMCU_APB1FZR

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Interpret as DBGMCU_APB1FZR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)TIM2 0 (B_0x0)TIM3 0 (B_0x0)TIM4 0 (B_0x0)TIM5 0 (B_0x0)TIM6 0 (B_0x0)TIM7 0 (B_0x0)TIM12 0 (B_0x0)TIM13 0 (B_0x0)TIM14 0 (B_0x0)LPTIM1 0 (B_0x0)WWDG 0 (B_0x0)I2C1 0 (B_0x0)I2C2 0 (B_0x0)I2C3

TIM14=B_0x0, WWDG=B_0x0, I2C3=B_0x0, I2C1=B_0x0, TIM13=B_0x0, I2C2=B_0x0, TIM7=B_0x0, TIM6=B_0x0, TIM5=B_0x0, TIM3=B_0x0, TIM12=B_0x0, LPTIM1=B_0x0, TIM2=B_0x0, TIM4=B_0x0

Description

DBGMCU APB1 peripheral freeze register

Fields

TIM2

TIM2 stop in debug

0 (B_0x0): Normal operation - TIM2 continues operating while the core is in Debug mode

1 (B_0x1): Stop in debug - TIM2 is frozen while Cortex-M7 is in Debug mode
TIM3

TIM3 stop in debug

0 (B_0x0): Normal operation - TIM3 continues operating while the core is in Debug mode

1 (B_0x1): Stop in debug - TIM3 is frozen while Cortex-M7 is in Debug mode
TIM4

TIM4 stop in debug

0 (B_0x0): Normal operation - TIM4 continues operating while the core is in Debug mode

1 (B_0x1): Stop in debug - TIM4 is frozen while Cortex-M7 is in Debug mode
TIM5

TIM5 stop in debug

0 (B_0x0): Normal operation - TIM5 continues operating while the core is in Debug mode

1 (B_0x1): Stop in debug - TIM5 is frozen while Cortex-M7 is in Debug mode
TIM6

TIM6 stop in debug

0 (B_0x0): Normal operation - TIM6 continues operating while the core is in Debug mode

1 (B_0x1): Stop in debug - TIM6 is frozen while Cortex-M7 is in Debug mode
TIM7

TIM7 stop in debug

0 (B_0x0): Normal operation - TIM7 continues operatinge while the core is in Debug mode

1 (B_0x1): Stop in debug - TIM7 is frozen while Cortex-M7 is in Debug mode
TIM12

TIM12 stop in debug

0 (B_0x0): Normal operation - TIM12 continues operatinge while the core is in Debug mode

1 (B_0x1): Stop in debug - TIM12 is frozen while Cortex-M7 is in Debug mode
TIM13

TIM13 stop in debug

0 (B_0x0): Normal operation - TIM13 continues operating while the core is in Debug mode

1 (B_0x1): Stop in debug - TIM13 is frozen while Cortex-M7 is in Debug mode
TIM14

TIM14 stop in debug

0 (B_0x0): Normal operation - TIM14 continues operating while the core is in Debug mode

1 (B_0x1): Stop in debug - TIM14 is frozen while Cortex-M7 is in Debug mode
LPTIM1

LPTIM1 stop in debug

0 (B_0x0): Normal operation - LPTIM1 continues operating while the core is in Debug mode

1 (B_0x1): Stop in debug - LPTIM1 is frozen while Cortex-M7 is in Debug mode
WWDG

WWDG stop in debug

0 (B_0x0): Normal operation - WWDG continues to operate while the Cortex-M7 is in Debug mode

1 (B_0x1): Stop in debug - WWDG is frozen while the Cortex-M7 is in Debug mode
I2C1

I2C1 SMBUS timeout stop in debug

0 (B_0x0): Normal operation - I2C1 SMBUS timeout continues operating while the core is in Debug mode

1 (B_0x1): Stop in debug - I2C1 SMBUS timeout is frozen while the core is in Debug mode
I2C2

I2C2 SMBUS timeout stop in debug

0 (B_0x0): Normal operation - I2C2 SMBUS timeout continues operating while the core is in Debug mode

1 (B_0x1): Stop in debug - I2C2 SMBUS timeout is frozen while Cortex-M7 is in Debug mode
I2C3

I2C3 SMBUS timeout stop in debug

0 (B_0x0): Normal operation - I2C3 SMBUS timeout continues operating while the core is in Debug mode

1 (B_0x1): Stop in debug - I2C3 SMBUS timeout is frozen while Cortex-M7 is in Debug mode

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32