DLYB_CR

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Interpret as DLYB_CR

SEN=B_0x0, DEN=B_0x0

DLYB control register

DEN	Delay block enable bit 0 (B_0x0): DLYB disabled. 1 (B_0x1): DLYB enabled.
SEN	Sampler length enable bit 0 (B_0x0): Sampler length and register access to UNIT[6:0] and SEL[3:0] disabled, output clock enabled. 1 (B_0x1): Sampler length and register access to UNIT[6:0] and SEL[3:0] enabled, output clock disabled.

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