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stm32 /stm32h7rs /STM32H7R /ETH /ETH_MMC_RX_INTERRUPT

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Interpret as ETH_MMC_RX_INTERRUPT

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RXCRCERPIS)RXCRCERPIS 0 (RXALGNERPIS)RXALGNERPIS 0 (RXUCGPIS)RXUCGPIS 0 (RXLPIUSCIS)RXLPIUSCIS 0 (RXLPITRCIS)RXLPITRCIS

Description

MMC Rx interrupt register

Fields

RXCRCERPIS

MMC Receive CRC Error Packet Counter Interrupt Status This bit is set when the Rx CRC error packets register (ETH_RX_CRC_ERROR_PACKETS) counter reaches half of the maximum value or the maximum value.
RXALGNERPIS

MMC Receive Alignment Error Packet Counter Interrupt Status This bit is set when the Rx alignment error packets register (ETH_RX_ALIGNMENT_ERROR_PACKETS) counter reaches half of the maximum value or the maximum value.
RXUCGPIS

MMC Receive Unicast Good Packet Counter Interrupt Status This bit is set when the Rx unicast packets good register (ETH_RX_UNICAST_PACKETS_GOOD) counter reaches half of the maximum value or the maximum value.
RXLPIUSCIS

MMC Receive LPI microsecond counter interrupt status This bit is set when the Rx LPI microsecond counter register (ETH_RX_LPI_USEC_CNTR) counter reaches half of the maximum value or the maximum value.
RXLPITRCIS

MMC Receive LPI transition counter interrupt status This bit is set when the Rx LPI transition counter register (ETH_RX_LPI_TRAN_CNTR) counter reaches half of the maximum value or the maximum value.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32