stm32 /stm32h7rs /STM32H7R /FDCAN1 /FDCAN_RXGFC

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Interpret as FDCAN_RXGFC

LSS=B_0x0, ANFS=B_0x0, RRFS=B_0x0, RRFE=B_0x0, LSE=B_0x0, ANFE=B_0x0

Description

FDCAN global filter configuration register

Fields

RRFE	Reject remote frames extended These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 0 (B_0x0): Filter remote frames with 29-bit standard IDs 1 (B_0x1): Reject all remote frames with 29-bit standard IDs
RRFS	Reject remote frames standard These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 0 (B_0x0): Filter remote frames with 11-bit standard IDs 1 (B_0x1): Reject all remote frames with 11-bit standard IDs
ANFE	Accept non-matching frames extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 0 (B_0x0): Accept in Rx FIFO 0 1 (B_0x1): Accept in Rx FIFO 1 2 (B_0x2): Reject 3 (B_0x3): Reject
ANFS	Accept Non-matching frames standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 0 (B_0x0): Accept in Rx FIFO 0 1 (B_0x1): Accept in Rx FIFO 1 2 (B_0x2): Reject 3 (B_0x3): Reject
F1OM	FIFO 1 operation mode (overwrite or blocking) This is a protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1.
F0OM	FIFO 0 operation mode (overwrite or blocking) This is protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1.
LSS	List size standard 1 to 28: Number of standard message ID filter elements 28: Values greater than 28 are interpreted as 28. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 0 (B_0x0): No standard message ID filter
LSE	List size extended 1 to 8: Number of extended message ID filter elements 8: Values greater than 8 are interpreted as 8. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 0 (B_0x0): No extended message ID filter

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