NBLW=B_0x00
HASH start register
| NBLW | Number of valid bits in the last word When the last word of the message bit string is written to HASH_DIN register, the hash processor takes only the valid bits, specified as below, after internal data swapping: … The above mechanism is valid only if DCAL = 0. If NBLW bits are written while DCAL is set to 1, the NBLW bitfield remains unchanged. In other words it is not possible to configure NBLW and set DCAL at the same time. Reading NBLW bits returns the last value written to NBLW. 0 (B_0x00): All the 32 bits of the last data written are valid message bits, that is M[31:0] 1 (B_0x01): Only one bit of the last data written (after swapping) is valid, that is M[0] 2 (B_0x02): Only two bits of the last data written (after swapping) are valid, that is M[1:0] 3 (B_0x03): Only three bits of the last data written (after swapping) are valid that is M[2:0] 31 (B_0x1F): Only 31 bits of the last data written (after swapping) are valid that is M[30:0] |
| DCAL | Digest calculation Writing this bit to 1 starts the message padding using the previously written value of NBLW, and starts the calculation of the final message digest with all the data words written to the input FIFO since the INIT bit was last written to 1. Reading this bit returns 0. |