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stm32 /stm32h7rs /STM32H7R /ICACHE /ICACHE_IER

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Interpret as ICACHE_IER

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)BSYENDIE 0 (B_0x0)ERRIE

BSYENDIE=B_0x0, ERRIE=B_0x0

Description

ICACHE interrupt enable register

Fields

BSYENDIE

interrupt enable on busy end Set by software to enable an interrupt generation at the end of a cache invalidate operation.

0 (B_0x0): interrupt disabled on busy end

1 (B_0x1): interrupt enabled on busy end
ERRIE

interrupt enable on cache error Set by software to enable an interrupt generation in case of cache functional error (cacheable write access)

0 (B_0x0): interrupt disabled on error

1 (B_0x1): interrupt enabled on error

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32