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stm32 /stm32h7rs /STM32H7R /SDMMC1 /SDMMC_DTIMER

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Interpret as SDMMC_DTIMER

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DATATIME

Description

SDMMC data timer register

Fields

DATATIME

Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32