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stm32 /stm32h7rs /STM32H7R /SDMMC1 /SDMMC_IDMACTRLR

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Interpret as SDMMC_IDMACTRLR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)IDMAEN 0 (B_0x0)IDMABMODE

IDMAEN=B_0x0, IDMABMODE=B_0x0

Description

SDMMC DMA control register

Fields

IDMAEN

IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0).

0 (B_0x0): IDMA disabled

1 (B_0x1): IDMA enabled
IDMABMODE

Buffer mode selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0).

0 (B_0x0): Single buffer mode.

1 (B_0x1): Linked list mode.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32