RXFIFOFIE=B_0x0, CMDSENTIE=B_0x0, CKSTOPIE=B_0x0, TXFIFOEIE=B_0x0, TXFIFOHEIE=B_0x0, DBCKENDIE=B_0x0, DHOLDIE=B_0x0, CCRCFAILIE=B_0x0, DCRCFAILIE=B_0x0, DABORTIE=B_0x0, SDIOITIE=B_0x0, IDMABTCIE=B_0x0, RXOVERRIE=B_0x0, DTIMEOUTIE=B_0x0, CTIMEOUTIE=B_0x0, BUSYD0ENDIE=B_0x0, DATAENDIE=B_0x0, CMDRENDIE=B_0x0, TXUNDERRIE=B_0x0, ACKTIMEOUTIE=B_0x0, VSWENDIE=B_0x0, ACKFAILIE=B_0x0, RXFIFOHFIE=B_0x0
SDMMC mask register
| CCRCFAILIE | Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure. 0 (B_0x0): Command CRC fail interrupt disabled 1 (B_0x1): Command CRC fail interrupt enabled |
| DCRCFAILIE | Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure. 0 (B_0x0): Data CRC fail interrupt disabled 1 (B_0x1): Data CRC fail interrupt enabled |
| CTIMEOUTIE | Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout. 0 (B_0x0): Command timeout interrupt disabled 1 (B_0x1): Command timeout interrupt enabled |
| DTIMEOUTIE | Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout. 0 (B_0x0): Data timeout interrupt disabled 1 (B_0x1): Data timeout interrupt enabled |
| TXUNDERRIE | Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error. 0 (B_0x0): Tx FIFO underrun error interrupt disabled 1 (B_0x1): Tx FIFO underrun error interrupt enabled |
| RXOVERRIE | Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error. 0 (B_0x0): Rx FIFO overrun error interrupt disabled 1 (B_0x1): Rx FIFO overrun error interrupt enabled |
| CMDRENDIE | Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response. 0 (B_0x0): Command response received interrupt disabled 1 (B_0x1): command Response received interrupt enabled |
| CMDSENTIE | Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command. 0 (B_0x0): Command sent interrupt disabled 1 (B_0x1): Command sent interrupt enabled |
| DATAENDIE | Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end. 0 (B_0x0): Data end interrupt disabled 1 (B_0x1): Data end interrupt enabled |
| DHOLDIE | Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state. 0 (B_0x0): Data hold interrupt disabled 1 (B_0x1): Data hold interrupt enabled |
| DBCKENDIE | Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end. 0 (B_0x0): Data block end interrupt disabled 1 (B_0x1): Data block end interrupt enabled |
| DABORTIE | Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted. 0 (B_0x0): Data transfer abort interrupt disabled 1 (B_0x1): Data transfer abort interrupt enabled |
| TXFIFOHEIE | Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty. 0 (B_0x0): Tx FIFO half empty interrupt disabled 1 (B_0x1): Tx FIFO half empty interrupt enabled |
| RXFIFOHFIE | Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full. 0 (B_0x0): Rx FIFO half full interrupt disabled 1 (B_0x1): Rx FIFO half full interrupt enabled |
| RXFIFOFIE | Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full. 0 (B_0x0): Rx FIFO full interrupt disabled 1 (B_0x1): Rx FIFO full interrupt enabled |
| TXFIFOEIE | Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty. 0 (B_0x0): Tx FIFO empty interrupt disabled 1 (B_0x1): Tx FIFO empty interrupt enabled |
| BUSYD0ENDIE | BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response. 0 (B_0x0): BUSYD0END interrupt disabled 1 (B_0x1): BUSYD0END interrupt enabled |
| SDIOITIE | SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt. 0 (B_0x0): SDIO Mode interrupt received interrupt disabled 1 (B_0x1): SDIO Mode interrupt received interrupt enabled |
| ACKFAILIE | Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail. 0 (B_0x0): Acknowledgment Fail interrupt disabled 1 (B_0x1): Acknowledgment Fail interrupt enabled |
| ACKTIMEOUTIE | Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout. 0 (B_0x0): Acknowledgment timeout interrupt disabled 1 (B_0x1): Acknowledgment timeout interrupt enabled |
| VSWENDIE | Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion. 0 (B_0x0): Voltage switch critical timing section completion interrupt disabled 1 (B_0x1): Voltage switch critical timing section completion interrupt enabled |
| CKSTOPIE | Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped. 0 (B_0x0): Voltage Switch clock stopped interrupt disabled 1 (B_0x1): Voltage Switch clock stopped interrupt enabled |
| IDMABTCIE | IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer. 0 (B_0x0): IDMA buffer transfer complete interrupt disabled 1 (B_0x1): IDMA buffer transfer complete interrupt enabled |