OVSS=B_0x0, ROVSM=B_0x0, TROVS=B_0x0, ROVSE=B_0x0, SWTRIG=B_0x0, OVSR=B_0x0, BULB=B_0x0, JOVSE=B_0x0, SMPTRIG=B_0x0
ADC configuration register 2
| ROVSE | Regular Oversampling Enable This bit is set and cleared by software to enable regular oversampling. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing) 0 (B_0x0): Regular Oversampling disabled 1 (B_0x1): Regular Oversampling enabled |
| JOVSE | Injected Oversampling Enable This bit is set and cleared by software to enable injected oversampling. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing) 0 (B_0x0): Injected Oversampling disabled 1 (B_0x1): Injected Oversampling enabled |
| OVSR | Oversampling ratio This bitfield is set and cleared by software to define the oversampling ratio. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no conversion is ongoing). 0 (B_0x0): 2x 1 (B_0x1): 4x 2 (B_0x2): 8x 3 (B_0x3): 16x 4 (B_0x4): 32x 5 (B_0x5): 64x 6 (B_0x6): 128x 7 (B_0x7): 256x |
| OVSS | Oversampling shift This bitfield is set and cleared by software to define the right shifting applied to the raw oversampling result. Other codes reserved Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no conversion is ongoing). 0 (B_0x0): No shift 1 (B_0x1): Shift 1-bit 2 (B_0x2): Shift 2-bits 3 (B_0x3): Shift 3-bits 4 (B_0x4): Shift 4-bits 5 (B_0x5): Shift 5-bits 6 (B_0x6): Shift 6-bits 7 (B_0x7): Shift 7-bits 8 (B_0x8): Shift 8-bits |
| TROVS | Triggered Regular Oversampling This bit is set and cleared by software to enable triggered oversampling Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). 0 (B_0x0): All oversampled conversions for a channel are done consecutively following a trigger 1 (B_0x1): Each oversampled conversion for a channel needs a new trigger |
| ROVSM | Regular Oversampling mode This bit is set and cleared by software to select the regular oversampling mode. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). 0 (B_0x0): Continued mode: When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence) 1 (B_0x1): Resumed mode: When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start) |
| SWTRIG | Software trigger bit for sampling time control trigger mode This bit is set and cleared by software to enable the bulb sampling mode. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). 0 (B_0x0): Software trigger starts the conversion for sampling time control trigger mode 1 (B_0x1): Software trigger starts the sampling for sampling time control trigger mode |
| BULB | Bulb sampling mode This bit is set and cleared by software to enable the bulb sampling mode. SAMPTRIG bit must not be set when the BULB bit is set. The very first ADC conversion is performed with the sampling time specified in SMPx bits. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). 0 (B_0x0): Bulb sampling mode disabled 1 (B_0x1): Bulb sampling mode enabled. The sampling period starts just after the previous end of conversion. |
| SMPTRIG | Sampling time control trigger mode This bit is set and cleared by software to enable the sampling time control trigger mode. The sampling time starts on the trigger rising edge, and the conversion on the trigger falling edge. EXTEN bit should be set to 01. BULB bit must not be set when the SMPTRIG bit is set. When EXTEN bit is set to 00, set SWTRIG to start the sampling and clear SWTRIG bit to start the conversion. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). 0 (B_0x0): Sampling time control trigger mode disabled 1 (B_0x1): Sampling time control trigger mode enabled |