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stm32 /stm32h7rs /STM32H7S /ADC1 /ADC_TR1

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Interpret as ADC_TR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0LT10 (B_0x0)AWDFILT 0HT1

AWDFILT=B_0x0

Description

ADC watchdog threshold register 1

Fields

LT1

Analog watchdog 1 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 1. Refer to Section 25.4.29: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).
AWDFILT

Analog watchdog filtering parameter This bit is set and cleared by software. … Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).

0 (B_0x0): No filtering

1 (B_0x1): two consecutive detection generates an AWDx flag or an interrupt

7 (B_0x7): Eight consecutive detection generates an AWDx flag or an interrupt
HT1

Analog watchdog 1 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 1. Refer to Section 25.4.29: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32