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stm32 /stm32h7rs /STM32H7S /ADC12_common /ADC_CDR

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Interpret as ADC_CDR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RDATA_MST0RDATA_SLV

Description

ADC common regular data register for dual mode

Fields

RDATA_MST

Regular data of the master ADC. In dual mode, these bits contain the regular data of the master ADC. Refer to Section 25.4.31: Dual ADC modes. The data alignment is applied as described in Section : Data register, data alignment and offset (ADC_DR, OFFSET, OFFSET_CH, ALIGN)) In MDMA = 0b11 mode, bits 15:8 contains SLV_ADC_DR[7:0], bits 7:0 contains MST_ADC_DR[7:0].
RDATA_SLV

Regular data of the slave ADC In dual mode, these bits contain the regular data of the slave ADC. Refer to Section 25.4.31: Dual ADC modes. The data alignment is applied as described in Section : Data register, data alignment and offset (ADC_DR, OFFSET, OFFSET_CH, ALIGN))

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32