TRGSENS=B_0x0, DMAEN=B_0x0, NBDIS=B_0x0, DFLTRUN=B_0x0, DFLTACTIVE=B_0x0, TRGSRC=B_0x0, DFLTEN=B_0x0, ACQMOD=B_0x0, FTH=B_0x0
ADF digital filter control register 0
| DFLTEN | DFLT0 enable This bit is set and cleared by software. It is used to control the start of acquisition of the DFLT0 path. This bit behavior depends on ACQMOD[2:0] and external events. The serial or parallel interface delivering the samples must be enabled as well. 0 (B_0x0): Acquisition immediately stopped 1 (B_0x1): Acquisition immediately started if ACQMOD[2:0] = 00x or 101, or acquisition started when the proper trigger event occurs if ACQMOD[2:0] = 01x. |
| DMAEN | DMA requests enable This bit is set and cleared by software. It is used to control the generation of DMA request to transfer the processed samples into the memory. Note: This bit can be write-protected (see Section 46.4.13: Register protection for details). 0 (B_0x0): DMA interface for the corresponding digital filter disabled 1 (B_0x1): DMA interface for the corresponding digital filter enabled |
| FTH | RXFIFO threshold selection This bit is set and cleared by software. It is used to select the RXFIFO threshold. Note: This bit can be write-protected (see Section 46.4.13: Register protection for details). 0 (B_0x0): RXFIFO threshold event generated when the RXFIFO is not empty 1 (B_0x1): RXFIFO threshold event generated when the RXFIFO is half-full |
| ACQMOD | DFLT0 trigger mode This field is set and cleared by software. It is used to select the filter trigger mode. others: same as 000 Note: This field can be write-protected (see Section 46.4.13: Register protection for details)… 0 (B_0x0): Asynchronous continuous acquisition mode 1 (B_0x1): Asynchronous single-shot acquisition mode 2 (B_0x2): Synchronous continuous acquisition mode 3 (B_0x3): Synchronous single-shot acquisition mode 4 (B_0x4): Window continuous acquisition mode |
| TRGSENS | DFLT0 trigger sensitivity selection This field is set and cleared by software. It is used to select the trigger sensitivity of the external signals When the trigger source is TRGO, TRGSENS value is not taken into account. When TRGO is selected, the sensitivity is forced to falling edge. Note: This bit can be write-protected (see Section 46.4.13: Register protection for details). 0 (B_0x0): A rising edge event triggers the acquisition. 1 (B_0x1): A falling edge even triggers the acquisition. |
| TRGSRC | DFLT0 trigger signal selection This field is set and cleared by software. It is used to select which external signals trigger DFLT0. others: Reserved Note: This field can be write-protected (see Section 46.4.13: Register protection for details). 0 (B_0x0): TRGO selected 2 (B_0x2): adf_trgi selected |
| NBDIS | Number of samples to be discarded This field is set and cleared by software. It is used to define the number of samples to be discarded every time DFLT0 is re-started. … Note: This field can be write-protected (see Section 46.4.13: Register protection for details). 0 (B_0x0): No sample discarded 1 (B_0x1): 1 sample discarded |
| DFLTRUN | DFLT0 run status flag This bit is set and cleared by hardware. It indicates if DFLT0 is running or not. 0 (B_0x0): DFLT0 not running and ready to accept a new trigger event 1 (B_0x1): DFLT0running |
| DFLTACTIVE | DFLT0 active flag This bit is set and cleared by hardware. It indicates if DFLT0 is active: can be running or waiting for events. 0 (B_0x0): DFLT0 not active (can be re-enabled again, via DFLTEN bit, if needed) 1 (B_0x1): DFLT0 active |