stm32 /stm32h7rs /STM32H7S /ADF /ADF_DLY0CR

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Interpret as ADF_DLY0CR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)SKPDLY0 (B_0x0)SKPBF

SKPBF=B_0x0, SKPDLY=B_0x0

Description

ADF delay control register 0

Fields

SKPDLY

Delay to apply to a bitstream This field is set and cleared by software. It defines the number of input samples that are skipped. Skipping is applied immediately after writing to this field, if SKPBF = 0 and DFLTEN = 1. If SKPBF = 1, the value written into the register is ignored by the delay state machine. …

0 (B_0x0): No input sample skipped

1 (B_0x1): 1 input sample skipped

SKPBF

Skip busy flag This bit is set and cleared by hardware. It is used to control if the delay sequence is completed.

0 (B_0x0): ADF ready to accept a new value into SKPDLY[6:0]

1 (B_0x1): Last valid SKPDLY[6:0] still under precessing

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