stm32 /stm32h7rs /STM32H7S /DCMIPP /DCMIPP_CMIER

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Interpret as DCMIPP_CMIER

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)ATXERRIE 0 (B_0x0)PRERRIE 0 (B_0x0)P0LINEIE 0 (B_0x0)P0FRAMEIE 0 (B_0x0)P0VSYNCIE 0 (B_0x0)P0LIMITIE 0 (B_0x0)P0OVRIE

P0OVRIE=B_0x0, ATXERRIE=B_0x0, P0LINEIE=B_0x0, P0LIMITIE=B_0x0, P0VSYNCIE=B_0x0, P0FRAMEIE=B_0x0, PRERRIE=B_0x0

Description

DCMIPP common interrupt enable register

Fields

ATXERRIE

AXI transfer error interrupt enable for IP-Plug

0 (B_0x0): No interrupt generation

1 (B_0x1): An interrupt is generated

PRERRIE

Limit interrupt enable for the parallel Interface

0 (B_0x0): No interrupt generation

1 (B_0x1): An interrupt is generated

P0LINEIE

Multi-line capture complete interrupt enable for Pipe0

0 (B_0x0): No interrupt generation

1 (B_0x1): An interrupt is generated

P0FRAMEIE

Frame capture complete interrupt enable for Pipe0

0 (B_0x0): No interrupt generation

1 (B_0x1): An interrupt is generated

P0VSYNCIE

Vertical sync interrupt enable for Pipe0

0 (B_0x0): No interrupt generation

1 (B_0x1): An interrupt is generated

P0LIMITIE

Limit interrupt enable for Pipe0

0 (B_0x0): No interrupt generation

1 (B_0x1): An interrupt is generated

P0OVRIE

Overrun interrupt enable for Pipe0

0 (B_0x0): No interrupt generation

1 (B_0x1): An interrupt is generated

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