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stm32 /stm32h7rs /STM32H7S /DCMIPP /DCMIPP_PRIER

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Interpret as DCMIPP_PRIER

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)ERRIE

ERRIE=B_0x0

Description

DCMIPP parallel interface interrupt enable register

Fields

ERRIE

Synchronization error interrupt enable This bit is available only in embedded synchronization mode.

0 (B_0x0): No interrupt generation

1 (B_0x1): An interrupt is generated if the embedded synchronization codes are not received in the correct order.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32