VSYNC=B_0x0, HSYNC=B_0x0, ERRF=B_0x0
DCMIPP parallel interface status register
| ERRF | Synchronization error raw interrupt status This bit is valid only in the embedded synchronization mode. It is cleared by writing a 1 to the CERRF bit in DCMIPP_PRFCR. This bit is available only in embedded synchronization mode. 0 (B_0x0): No synchronization error detected 1 (B_0x1): Embedded synchronization characters are not received in the correct order. |
| HSYNC | This bit gives the state of the HSYNC pin with the correct programmed polarity if ENABLE bit is set into the DCMIPP_PRCR register and if the pixel clock is received. It is set during the blanking period whatever the polarity selected in HPOL bit, and cleared otherwise. When embedded synchronization codes are used: In case of embedded synchronization, this bit is meaningful only if the CAPTURE bit in DCMIPP_CR is set. 0 (B_0x0): Active line 1 (B_0x1): Synchronization between lines |
| VSYNC | This bit gives the state of the VSYNC pin with the correct programmed polarity if ENABLE bit is set into the DCMIPP_PRCR register and if the pixel clock is received. It is set during the blanking period whatever the polarity selected in VPOL bit, and cleared otherwise. When embedded synchronization codes are used: In case of embedded synchronization, this bit is meaningful only if the CAPTURE bit in DCMIPP_CR is set. 0 (B_0x0): Active frame 1 (B_0x1): Synchronization between frames |