AI=B_0x0, CM=B_0x0, AM=B_0x0, RBS=B_0x0, CCM=B_0x0
DMA2D background PFC control register
| CM | Color mode These bits define the color format of the foreground image. Others: Reserved 0 (B_0x0): ARGB8888 1 (B_0x1): RGB888 2 (B_0x2): RGB565 3 (B_0x3): ARGB1555 4 (B_0x4): ARGB4444 5 (B_0x5): L8 6 (B_0x6): AL44 7 (B_0x7): AL88 8 (B_0x8): L4 9 (B_0x9): A8 10 (B_0xA): A4 |
| CCM | CLUT color mode These bits define the color format of the CLUT. 0 (B_0x0): ARGB8888 1 (B_0x1): RGB888 |
| START | Start This bit is set to start the automatic loading of the CLUT. This bit is automatically reset: at the end of the transfer when the transfer is aborted by the user by setting ABORT bit in DMA2D_CR when a transfer error occurs when the transfer has not started due to a configuration error or another transfer operation already on going (data transfer or automatic background CLUT transfer) |
| CS | CLUT size These bits define the size of the CLUT used for the BG. The number of CLUT entries is equal to CS[7:0] + 1. |
| AM | Alpha mode These bits define which alpha channel value to be used for the background image. Others: Reserved 0 (B_0x0): No modification of the foreground image alpha channel value 1 (B_0x1): Replace original background image alpha channel value by ALPHA[7: 0] 2 (B_0x2): Replace original background image alpha channel value by ALPHA[7:0] multiplied with original alpha channel value |
| AI | Alpha Inverted This bit inverts the alpha value. 0 (B_0x0): Regular alpha 1 (B_0x1): Inverted alpha |
| RBS | Red/Blue swap This bit allows to swap Red and Blue to support BGR or ABGR color formats. 0 (B_0x0): Regular mode (RGB or ARGB) 1 (B_0x1): Swap mode (BGR or ABGR) |
| ALPHA | Alpha value These bits define a fixed alpha channel value which can replace the original alpha value, or be multiplied with the original alpha value according to the alpha mode selected with AM[1:0]. |