CAEIE=B_0x0, MODE=B_0x0, CTCIE=B_0x0, TCIE=B_0x0, SUSP=B_0x0, LOM=B_0x0, TWIE=B_0x0, ABORT=B_0x0, TEIE=B_0x0, CEIE=B_0x0
DMA2D control register
| START | Start This bit can be used to launch the DMA2D according to parameters loaded in the various configuration registers. This bit is automatically reset by the following events: at the end of the transfer when the data transfer is aborted by the user by setting ABORT in this register when a data transfer error occurs when the data transfer has not started due to a configuration error, or another transfer operation already ongoing (automatic CLUT loading) |
| SUSP | Suspend This bit can be used to suspend the current transfer. This bit is set and reset by software. It is automatically reset by hardware when START = 0. 0 (B_0x0): Transfer not suspended 1 (B_0x1): Transfer suspended |
| ABORT | Abort This bit can be used to abort the current transfer. This bit is set by software, and is automatically reset by hardware when START = 0. 0 (B_0x0): No transfer abort requested 1 (B_0x1): Transfer abort requested |
| LOM | Line offset mode This bit configures how the line offset is expressed (pixels or bytes) for the foreground, background and output. This bit is set and cleared by software. It can not be modified while a transfer is ongoing. 0 (B_0x0): Line offsets expressed in pixels 1 (B_0x1): Line offsets expressed in bytes |
| TEIE | Transfer error (TE) interrupt enable This bit is set and cleared by software. 0 (B_0x0): TE interrupt disabled 1 (B_0x1): TE interrupt enabled |
| TCIE | Transfer complete (TC) interrupt enable This bit is set and cleared by software. 0 (B_0x0): TC interrupt disabled 1 (B_0x1): TC interrupt enabled |
| TWIE | Transfer watermark (TW) interrupt enable This bit is set and cleared by software. 0 (B_0x0): TW interrupt disabled 1 (B_0x1): TW interrupt enabled |
| CAEIE | CLUT access error (CAE) interrupt enable This bit is set and cleared by software. 0 (B_0x0): CAE interrupt disabled 1 (B_0x1): CAE interrupt enabled |
| CTCIE | CLUT transfer complete (CTC) interrupt enable This bit is set and cleared by software. 0 (B_0x0): CTC interrupt disabled 1 (B_0x1): CTC interrupt enabled |
| CEIE | Configuration error (CE) interrupt enable This bit is set and cleared by software. 0 (B_0x0): CE interrupt disabled 1 (B_0x1): CE interrupt enabled |
| MODE | DMA2D mode This bit is set and cleared by software. It cannot be modified while a transfer is ongoing. Others: Reserved 0 (B_0x0): Memory-to-memory (FG fetch only) 1 (B_0x1): Memory-to-memory with PFC (FG fetch only with FG PFC active) 2 (B_0x2): Memory-to-memory with blending (FG and BG fetch with PFC and blending) 3 (B_0x3): Register-to-memory (no FG nor BG, only output stage active) 4 (B_0x4): Memory-to-memory with blending and fixed color FG (BG fetch only with FG and BG PFC active) 5 (B_0x5): Memory-to-memory with blending and fixed color BG (FG fetch only with FG and BG PFC active) |