TFCSTS=B_0x0
Debug register
| RPESTS | MAC MII Receive Protocol Engine Status When this bit is set, it indicates that the MAC MII receive protocol engine is actively receiving data, and it is not in the Idle state. |
| RFCFCSTS | MAC Receive Packet Controller FIFO Status When this bit is set, this field indicates the active state of the small FIFO Read and Write controllers of the MAC Receive Packet Controller module. |
| TPESTS | MAC MII Transmit Protocol Engine Status When this bit is set, it indicates that the MAC MII transmit protocol engine is actively transmitting data, and it is not in the Idle state. |
| TFCSTS | MAC Transmit Packet Controller Status This field indicates the state of the MAC Transmit Packet Controller module: Status of the previous packet IPG or backoff period to be over 0 (B_0x0): Idle state 1 (B_0x1): Waiting for one of the following: 2 (B_0x2): Generating and transmitting a Pause control packet (in Full-duplex mode) 3 (B_0x3): Transferring input packet for transmission |