TRGTMODSEL0=B_0x0
PPS control register
| PPSCTRL | PPS Output Frequency Control This field controls the frequency of the PPS output (eth_ptp_pps_out) signal. The default value of PPSCTRL is 0000, and the PPS output is 1 pulse (of width clk_ptp_i) every second. For other values of PPSCTRL, the PPS output becomes a generated clock of following frequencies: … Note: In the binary rollover mode, the PPS output (eth_ptp_pps_out) has a duty cycle of 50 percent with these frequencies. In the digital rollover mode, the PPS output frequency is an average number. The actual clock is of different frequency that gets synchronized every second. For example: When PPSCTRL = 0001, the PPS (1 Hz) has a low period of 537 ms and a high period of 463 ms When PPSCTRL = 0010, the PPS (2 Hz) is a sequence of One clock of 50 percent duty cycle and 537 ms period Second clock of 463 ms period (268 ms low and 195 ms high) When PPSCTRL = 0011, the PPS (4 Hz) is a sequence of Three clocks of 50 percent duty cycle and 268 ms period Fourth clock of 195 ms period (134 ms low and 61 ms high) This behavior is because of the non-linear toggling of bits in the digital rollover mode in the ETH_MACSTNR register. 1 (B_0x1): The binary rollover is 2 Hz, and the digital rollover is 1 Hz. 2 (B_0x2): The binary rollover is 4 Hz, and the digital rollover is 2 Hz. 3 (B_0x3): The binary rollover is 8 Hz, and the digital rollover is 4 Hz. 4 (B_0x4): The binary rollover is 16 Hz, and the digital rollover is 8 Hz. 15 (B_0xF): The binary rollover is 32.768 KHz and the digital rollover is 16.384 KHz. |
| PPSEN0 | Flexible PPS Output Mode Enable When this bit is set, PPSCTRL[3:0] function as PPSCMD[3:0]. When this bit is reset, PPSCTRL[3:0] function as PPSCTRL (Fixed PPS mode). |
| TRGTMODSEL0 | Target Time Register Mode for PPS Output This field indicates the Target Time registers (PPS target time seconds register (ETH_MACPPSTTSR) and PPS target time nanoseconds register (ETH_MACPPSTTNR)) mode for PPS output signal: 0 (B_0x0): Target Time registers are programmed only for generating the interrupt event. 1 (B_0x1): Reserved, must not be used 2 (B_0x2): Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS output signal generation. 3 (B_0x3): Target Time registers are programmed only for starting or stopping the PPS output signal generation. No interrupt is asserted. |