MR8=B_0x0, MR25=B_0x0, MR14=B_0x0, MR2=B_0x0, MR22=B_0x0, MR0=B_0x0, MR16=B_0x0, MR5=B_0x0, MR9=B_0x0, MR27=B_0x0, MR23=B_0x0, MR18=B_0x0, MR1=B_0x0, MR21=B_0x0, MR20=B_0x0, MR7=B_0x0, MR19=B_0x0, MR31=B_0x0, MR12=B_0x0, MR17=B_0x0, MR15=B_0x0, MR11=B_0x0, MR3=B_0x0, MR29=B_0x0, MR26=B_0x0, MR6=B_0x0, MR4=B_0x0, MR30=B_0x0, MR24=B_0x0, MR13=B_0x0, MR28=B_0x0, MR10=B_0x0
EXTI event mask register
MR0 | CPU event mask on event input x 0 (B_0x0): Event request from line x is masked 1 (B_0x1): Event request from line x is unmasked |
MR1 | CPU event mask on event input x 0 (B_0x0): Event request from line x is masked 1 (B_0x1): Event request from line x is unmasked |
MR2 | CPU event mask on event input x 0 (B_0x0): Event request from line x is masked 1 (B_0x1): Event request from line x is unmasked |
MR3 | CPU event mask on event input x 0 (B_0x0): Event request from line x is masked 1 (B_0x1): Event request from line x is unmasked |
MR4 | CPU event mask on event input x 0 (B_0x0): Event request from line x is masked 1 (B_0x1): Event request from line x is unmasked |
MR5 | CPU event mask on event input x 0 (B_0x0): Event request from line x is masked 1 (B_0x1): Event request from line x is unmasked |
MR6 | CPU event mask on event input x 0 (B_0x0): Event request from line x is masked 1 (B_0x1): Event request from line x is unmasked |
MR7 | CPU event mask on event input x 0 (B_0x0): Event request from line x is masked 1 (B_0x1): Event request from line x is unmasked |
MR8 | CPU event mask on event input x 0 (B_0x0): Event request from line x is masked 1 (B_0x1): Event request from line x is unmasked |
MR9 | CPU event mask on event input x 0 (B_0x0): Event request from line x is masked 1 (B_0x1): Event request from line x is unmasked |
MR10 | CPU event mask on event input x 0 (B_0x0): Event request from line x is masked 1 (B_0x1): Event request from line x is unmasked |
MR11 | CPU event mask on event input x 0 (B_0x0): Event request from line x is masked 1 (B_0x1): Event request from line x is unmasked |
MR12 | CPU event mask on event input x 0 (B_0x0): Event request from line x is masked 1 (B_0x1): Event request from line x is unmasked |
MR13 | CPU event mask on event input x 0 (B_0x0): Event request from line x is masked 1 (B_0x1): Event request from line x is unmasked |
MR14 | CPU event mask on event input x 0 (B_0x0): Event request from line x is masked 1 (B_0x1): Event request from line x is unmasked |
MR15 | CPU event mask on event input x 0 (B_0x0): Event request from line x is masked 1 (B_0x1): Event request from line x is unmasked |
MR16 | CPU event mask on event input x 0 (B_0x0): Event request from line x is masked 1 (B_0x1): Event request from line x is unmasked |
MR17 | CPU event mask on event input x 0 (B_0x0): Event request from line x is masked 1 (B_0x1): Event request from line x is unmasked |
MR18 | CPU event mask on event input x 0 (B_0x0): Event request from line x is masked 1 (B_0x1): Event request from line x is unmasked |
MR19 | CPU event mask on event input x 0 (B_0x0): Event request from line x is masked 1 (B_0x1): Event request from line x is unmasked |
MR20 | CPU event mask on event input x 0 (B_0x0): Event request from line x is masked 1 (B_0x1): Event request from line x is unmasked |
MR21 | CPU event mask on event input x 0 (B_0x0): Event request from line x is masked 1 (B_0x1): Event request from line x is unmasked |
MR22 | CPU event mask on event input x 0 (B_0x0): Event request from line x is masked 1 (B_0x1): Event request from line x is unmasked |
MR23 | CPU event mask on event input x 0 (B_0x0): Event request from line x is masked 1 (B_0x1): Event request from line x is unmasked |
MR24 | CPU event mask on event input x 0 (B_0x0): Event request from line x is masked 1 (B_0x1): Event request from line x is unmasked |
MR25 | CPU event mask on event input x 0 (B_0x0): Event request from line x is masked 1 (B_0x1): Event request from line x is unmasked |
MR26 | CPU event mask on event input x 0 (B_0x0): Event request from line x is masked 1 (B_0x1): Event request from line x is unmasked |
MR27 | CPU event mask on event input x 0 (B_0x0): Event request from line x is masked 1 (B_0x1): Event request from line x is unmasked |
MR28 | CPU event mask on event input x 0 (B_0x0): Event request from line x is masked 1 (B_0x1): Event request from line x is unmasked |
MR29 | CPU event mask on event input x 0 (B_0x0): Event request from line x is masked 1 (B_0x1): Event request from line x is unmasked |
MR30 | CPU event mask on event input x 0 (B_0x0): Event request from line x is masked 1 (B_0x1): Event request from line x is unmasked |
MR31 | CPU event mask on event input x 0 (B_0x0): Event request from line x is masked 1 (B_0x1): Event request from line x is unmasked |