MR33=B_0x0, MR59=B_0x0, MR41=B_0x0, MR44=B_0x0, MR49=B_0x0, MR38=B_0x0, MR37=B_0x0, MR48=B_0x0, MR42=B_0x0, MR35=B_0x0, MR32=B_0x0, MR40=B_0x0, MR54=B_0x0, MR46=B_0x0, MR57=B_0x0, MR56=B_0x0, MR53=B_0x0, MR55=B_0x0, MR52=B_0x0, MR43=B_0x0, MR45=B_0x0, MR58=B_0x0, MR39=B_0x0, MR36=B_0x0, MR34=B_0x0, MR51=B_0x0, MR47=B_0x0, MR50=B_0x0
EXTI event mask register
| MR32 | CPU event mask on event input i 0 (B_0x0): Event request from line 32 is masked 1 (B_0x1): Event request from line 32 is unmasked |
| MR33 | CPU event mask on event input i 0 (B_0x0): Event request from line 33 is masked 1 (B_0x1): Event request from line 33 is unmasked |
| MR34 | CPU event mask on event input i 0 (B_0x0): Event request from line 34 is masked 1 (B_0x1): Event request from line 34 is unmasked |
| MR35 | CPU event mask on event input i 0 (B_0x0): Event request from line 35 is masked 1 (B_0x1): Event request from line 35 is unmasked |
| MR36 | CPU event mask on event input i 0 (B_0x0): Event request from line 36 is masked 1 (B_0x1): Event request from line 36 is unmasked |
| MR37 | CPU event mask on event input i 0 (B_0x0): Event request from line 37 is masked 1 (B_0x1): Event request from line 37 is unmasked |
| MR38 | CPU event mask on event input i 0 (B_0x0): Event request from line 38 is masked 1 (B_0x1): Event request from line 38 is unmasked |
| MR39 | CPU event mask on event input i 0 (B_0x0): Event request from line 39 is masked 1 (B_0x1): Event request from line 39 is unmasked |
| MR40 | CPU event mask on event input i 0 (B_0x0): Event request from line 40 is masked 1 (B_0x1): Event request from line 40 is unmasked |
| MR41 | CPU event mask on event input i 0 (B_0x0): Event request from line 41 is masked 1 (B_0x1): Event request from line 41 is unmasked |
| MR42 | CPU event mask on event input i 0 (B_0x0): Event request from line 42 is masked 1 (B_0x1): Event request from line 42 is unmasked |
| MR43 | CPU event mask on event input i 0 (B_0x0): Event request from line 43 is masked 1 (B_0x1): Event request from line 43 is unmasked |
| MR44 | CPU event mask on event input i 0 (B_0x0): Event request from line 44 is masked 1 (B_0x1): Event request from line 44 is unmasked |
| MR45 | CPU event mask on event input i 0 (B_0x0): Event request from line 45 is masked 1 (B_0x1): Event request from line 45 is unmasked |
| MR46 | CPU event mask on event input i 0 (B_0x0): Event request from line 46 is masked 1 (B_0x1): Event request from line 46 is unmasked |
| MR47 | CPU event mask on event input i 0 (B_0x0): Event request from line 47 is masked 1 (B_0x1): Event request from line 47 is unmasked |
| MR48 | CPU event mask on event input i 0 (B_0x0): Event request from line 48 is masked 1 (B_0x1): Event request from line 48 is unmasked |
| MR49 | CPU event mask on event input i 0 (B_0x0): Event request from line 49 is masked 1 (B_0x1): Event request from line 49 is unmasked |
| MR50 | CPU event mask on event input i 0 (B_0x0): Event request from line 50 is masked 1 (B_0x1): Event request from line 50 is unmasked |
| MR51 | CPU event mask on event input i 0 (B_0x0): Event request from line 51 is masked 1 (B_0x1): Event request from line 51 is unmasked |
| MR52 | CPU event mask on event input i 0 (B_0x0): Event request from line 52 is masked 1 (B_0x1): Event request from line 52 is unmasked |
| MR53 | CPU event mask on event input i 0 (B_0x0): Event request from line 53 is masked 1 (B_0x1): Event request from line 53 is unmasked |
| MR54 | CPU event mask on event input i 0 (B_0x0): Event request from line 54 is masked 1 (B_0x1): Event request from line 54 is unmasked |
| MR55 | CPU event mask on event input i 0 (B_0x0): Event request from line 55 is masked 1 (B_0x1): Event request from line 55 is unmasked |
| MR56 | CPU event mask on event input i 0 (B_0x0): Event request from line 56 is masked 1 (B_0x1): Event request from line 56 is unmasked |
| MR57 | CPU event mask on event input i 0 (B_0x0): Event request from line 57 is masked 1 (B_0x1): Event request from line 57 is unmasked |
| MR58 | CPU event mask on event input i 0 (B_0x0): Event request from line 58 is masked 1 (B_0x1): Event request from line 58 is unmasked |
| MR59 | CPU event mask on event input i 0 (B_0x0): Event request from line 59 is masked 1 (B_0x1): Event request from line 59 is unmasked |