stm32 /stm32h7rs /STM32H7S /FLASH /FLASH_OBW1SR

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Interpret as FLASH_OBW1SR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)BOR_LEV 0 (B_0x0)IWDG_HW 0 (B_0x0)NRST_STOP 0 (B_0x0)NRST_STBY 0 (B_0x0)OCTO1_HSLV 0 (B_0x0)OCTO2_HSLV 0 (B_0x0)IWDG_FZ_STOP 0 (B_0x0)IWDG_FZ_SDBY 0 (PERSO_OK)PERSO_OK 0 (B_0x0)VDDIO_HSLV

BOR_LEV=B_0x0, OCTO2_HSLV=B_0x0, OCTO1_HSLV=B_0x0, IWDG_HW=B_0x0, NRST_STOP=B_0x0, IWDG_FZ_SDBY=B_0x0, VDDIO_HSLV=B_0x0, NRST_STBY=B_0x0, IWDG_FZ_STOP=B_0x0

Description

FLASH option byte word 1 status register

Fields

BOR_LEV

Brownout level These bits reflects the power level that generates a system reset.

0 (B_0x0): BOR OFF, POR/PDR reset threshold level is applied

1 (B_0x1): BOR Level 1, the threshold level is low (around 2.1 V)

2 (B_0x2): BOR Level 2, the threshold level is medium (around 2.4 V)

3 (B_0x3): BOR Level 3, the threshold level is high (around 2.7 V)

IWDG_HW

Independent watchdog HW Control

0 (B_0x0): IWDG watchdog is controller by hardware

1 (B_0x1): IWDG watchdog is controlled by software

NRST_STOP

Reset on stop mode

0 (B_0x0): Independent WDG generates a reset if STOP mode is requested

1 (B_0x1): Independent WDG does not generate a reset if STOP mode is requested

NRST_STBY

Reset on standby mode

0 (B_0x0): Independent WDG generates a reset if STANDBY mode is requested

1 (B_0x1): Independent WDG does not generate a reset if STANDBY mode is requested

OCTO1_HSLV

XSPIM_P1 High-Speed at Low-Voltage

0 (B_0x0): I/O XSPIM_P1 High-Speed option disabled

1 (B_0x1): I/O XSPIM_P1 High-Speed option enabled

OCTO2_HSLV

XSPIM_P2 High-Speed at Low-Voltage

0 (B_0x0): I/O XSPIM_P2 High-Speed option disabled

1 (B_0x1): I/O XSPIM_P2 High-Speed option enabled

IWDG_FZ_STOP

IWDG stop mode freeze When set the independent watchdog IWDG is frozen in system Stop mode.

0 (B_0x0): Independent watchdog frozen in Stop mode

1 (B_0x1): Independent watchdog keep running in Stop mode

IWDG_FZ_SDBY

IWDG standby mode freeze When set the independent watchdog IWDG is frozen in system Standby mode.

0 (B_0x0): Independent watchdog frozen in Standby mode

1 (B_0x1): Independent watchdog keep running in Standby mode

PERSO_OK

Personalization OK This bit is set on STMicroelectronics production line.

VDDIO_HSLV

I/O High-Speed at Low-Voltage This bit indicates that the product operates below 2.5 V.

0 (B_0x0): Product working in the full voltage range, I/O speed optimization at low-voltage disabled

1 (B_0x1): Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed

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