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stm32 /stm32h7rs /STM32H7S /FLASH /FLASH_OBW1SRP

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Interpret as FLASH_OBW1SRP

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0BOR_LEV 0 (IWDG_HW)IWDG_HW 0 (NRST_STOP)NRST_STOP 0 (NRST_STBY)NRST_STBY 0 (OCTO1_HSLV)OCTO1_HSLV 0 (OCTO2_HSLV)OCTO2_HSLV 0 (IWDG_FZ_STOP)IWDG_FZ_STOP 0 (IWDG_FZ_SDBY)IWDG_FZ_SDBY 0 (VDDIO_HSLV)VDDIO_HSLV

Description

FLASH option byte word 1 status register programming

Fields

BOR_LEV

Brownout level Write to change corresponding bits in FLASH_OBW1SR register.
IWDG_HW

Independent watchdog HW Control Write to change corresponding bit in FLASH_OBW1SR register.
NRST_STOP

Reset on stop mode programming Write to change corresponding bit in FLASH_OBW1SR register.
NRST_STBY

Reset on standby mode programming Write to change corresponding bit in FLASH_OBW1SR register.
OCTO1_HSLV

XSPIM_P1 High-Speed at Low-Voltage Write to change corresponding bit in FLASH_OBW1SR register.
OCTO2_HSLV

XSPIM_P2 High-Speed at Low-Voltage programming Write to change corresponding bit in FLASH_OBW1SR register.
IWDG_FZ_STOP

IWDG stop mode freeze Write to change corresponding bit in FLASH_OBW1SR register.
IWDG_FZ_SDBY

IWDG standby mode freeze programming Write to change corresponding bit in FLASH_OBW1SR register.
VDDIO_HSLV

I/O High-Speed at Low-Voltage programming Write to change corresponding bit in FLASH_OBW1SR register.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32