PWAITEN=B_0x0, TCLR=B_0x0, TAR2=B_0x0, PBKEN=B_0x0, ECCPS=B_0x0, TAR1=B_0x0, TAR0=B_0x0, ECCEN=B_0x0, TAR3=B_0x0, PWID=B_0x0
NAND flash control registers
| PWAITEN | Wait feature enable bit. This bit enables the Wait feature for the NAND flash memory bank: 0 (B_0x0): disabled 1 (B_0x1): enabled |
| PBKEN | NAND flash memory bank enable bit. This bit enables the memory bank. Accessing a disabled memory bank causes an ERROR on AXI bus 0 (B_0x0): Corresponding memory bank is disabled (default after reset) 1 (B_0x1): Corresponding memory bank is enabled |
| PWID | Data bus width. These bits define the external memory device width. 0 (B_0x0): 8 bits 1 (B_0x1): 16 bits (default after reset). 2 (B_0x2): reserved. 3 (B_0x3): reserved. |
| ECCEN | ECC computation logic enable bit 0 (B_0x0): ECC logic is disabled and reset (default after reset), 1 (B_0x1): ECC logic is enabled. |
| TCLR | CLE to RE delay. These bits set time from CLE low to RE low in number of fmc_ker_ck clock cycles. The time is give by the following formula: t_clr = (TCLR + SET + 2) tfmc_ker_ck where tfmc_ker_ck is the fmc_ker_ck clock period Note: Set is MEMSET or ATTSET according to the addressed space. 0 (B_0x0): 1 x fmc_ker_ck cycle (default) 15 (B_0xF): 16 x fmc_ker_ck cycles |
| TAR0 | ALE to RE delay. These bits set time from ALE low to RE low in number of fmc_ker_ck clock cycles. Time is: t_ar = (TAR + SET + 2) tfmc_ker_ck where tfmc_ker_ck is the FMC clock period Note: Set is MEMSET or ATTSET according to the addressed space. 0 (B_0x0): 1 x fmc_ker_ck cycle (default) |
| TAR1 | ALE to RE delay. These bits set time from ALE low to RE low in number of fmc_ker_ck clock cycles. Time is: t_ar = (TAR + SET + 2) tfmc_ker_ck where tfmc_ker_ck is the FMC clock period Note: Set is MEMSET or ATTSET according to the addressed space. 0 (B_0x0): 1 x fmc_ker_ck cycle (default) |
| TAR2 | ALE to RE delay. These bits set time from ALE low to RE low in number of fmc_ker_ck clock cycles. Time is: t_ar = (TAR + SET + 2) tfmc_ker_ck where tfmc_ker_ck is the FMC clock period Note: Set is MEMSET or ATTSET according to the addressed space. 0 (B_0x0): 1 x fmc_ker_ck cycle (default) |
| TAR3 | ALE to RE delay. These bits set time from ALE low to RE low in number of fmc_ker_ck clock cycles. Time is: t_ar = (TAR + SET + 2) tfmc_ker_ck where tfmc_ker_ck is the FMC clock period Note: Set is MEMSET or ATTSET according to the addressed space. 0 (B_0x0): 1 x fmc_ker_ck cycle (default) |
| ECCPS | ECC page size. These bits define the page size for the extended ECC: 0 (B_0x0): 256 bytes 1 (B_0x1): 512 bytes 2 (B_0x2): 1024 bytes 3 (B_0x3): 2048 bytes 4 (B_0x4): 4096 bytes 5 (B_0x5): 8192 bytes |