CRE=B_0x0, REIE=B_0x0
SDRAM refresh timer register
| CRE | Clear Refresh error flag This bit is used to clear the Refresh Error Flag (RE) in the Status Register. 0 (B_0x0): no effect 1 (B_0x1): Refresh Error flag is cleared |
| COUNT | Refresh Timer Count This 13-bit field defines the refresh rate of the SDRAM device. It is expressed in number of memory clock cycles. It must be set at least to 41 SDRAM clock cycles (0x29). Refresh rate = (COUNT + 1) x SDRAM frequency clock COUNT = (SDRAM refresh period / Number of rows) - 20 |
| REIE | RES Interrupt Enable 0 (B_0x0): Interrupt is disabled 1 (B_0x1): An Interrupt is generated if RE = 1 |