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stm32 /stm32h7rs /STM32H7S /LTDC /LTDC_CDSR

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Interpret as LTDC_CDSR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)VDES 0 (B_0x0)HDES 0 (B_0x0)VSYNCS 0 (B_0x0)HSYNCS

HSYNCS=B_0x0, HDES=B_0x0, VDES=B_0x0, VSYNCS=B_0x0

Description

LTDC current display status register

Fields

VDES

vertical data enable display status

0 (B_0x0): active low

1 (B_0x1): active high
HDES

horizontal data enable display status

0 (B_0x0): active low

1 (B_0x1): active high
VSYNCS

vertical synchronization display status

0 (B_0x0): active low

1 (B_0x1): active high
HSYNCS

horizontal synchronization display status

0 (B_0x0): active low

1 (B_0x1): active high

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32