stm32 /stm32h7rs /STM32H7S /OTG_HS /OTG_DSTS

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Interpret as OTG_DSTS

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SUSPSTS)SUSPSTS 0 (B_0x0)ENUMSPD 0 (EERR)EERR 0FNSOF0DEVLNSTS

ENUMSPD=B_0x0

Description

OTG device status register

Fields

SUSPSTS

Suspend status In device mode, this bit is set as long as a suspend condition is detected on the USB. The core enters the suspended state when there is no activity on the USB data lines for a period of 3 ms. The core comes out of the suspend: When there is an activity on the USB data lines When the application writes to the remote wakeup signaling bit in the OTG_DCTL register (RWUSIG bit in OTG_DCTL).

ENUMSPD

Enumerated speed Indicates the speed at which the OTG_HS controller has come up after speed detection through a chirp sequence. Others: reserved

0 (B_0x0): High Speed

1 (B_0x1): Full Speed

3 (B_0x3): FIELD Reserved

EERR

Erratic error The core sets this bit to report any erratic errors. Due to erratic errors, the OTG_HS controller goes into suspended state and an interrupt is generated to the application with Early suspend bit of the OTG_GINTSTS register (ESUSP bit in OTG_GINTSTS). If the early suspend is asserted due to an erratic error, the application can only perform a soft disconnect recover.

FNSOF

Frame number of the received SOF

DEVLNSTS

Device line status Indicates the current logic level USB data lines. Bit [23]: Logic level of D+ Bit [22]: Logic level of D-

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