PHYLPC=B_0x0, FDMOD=B_0x0, TSDPS=B_0x0, FHMOD=B_0x0
OTG USB configuration register
| TOCAL | FS timeout calibration The number of PHY clocks that the application programs in this field is added to the full-speed interpacket timeout duration in the core to account for any additional delays introduced by the PHY. This can be required, because the delay introduced by the PHY in generating the line state condition can vary from one PHY to another. The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The application must program this field based on the speed of enumeration. The number of bit times added per PHY clock is 0.25 bit times. |
| TRDT | USB turnaround time These bits allows to set the turnaround time in PHY clocks. They must be configured according to Table 683: TRDT values, depending on the application AHB frequency. Higher TRDT values allow stretching the USB response time to IN tokens in order to compensate for longer AHB read access latency to the data FIFO. Note: Only accessible in device mode. |
| PHYLPC | PHY Low-power clock select This bit selects either 480 MHz or 48 MHz (low-power) PHY mode. In FS and LS modes, the PHY can usually operate on a 48 MHz clock to save power. In 480 MHz mode, the UTMI interface operates at either 60 or 30 MHz, depending on whether the 8- or 16-bit data width is selected. In 48 MHz mode, the UTMI interface operates at 48 MHz in FS and LS modes. 0 (B_0x0): 480 MHz internal PLL clock 1 (B_0x1): 48 MHz external clock |
| TSDPS | TermSel DLine pulsing selection This bit selects utmi_termselect to drive the data line pulse during SRP (session request protocol). 0 (B_0x0): Data line pulsing using utmi_txvalid (default) 1 (B_0x1): Data line pulsing using utmi_termsel |
| FHMOD | Force host mode Writing a 1 to this bit, forces the core to host mode irrespective of the OTG_ID input pin. After setting the force bit, the application must wait at least 25 ms before the change takes effect. Note: Accessible in both device and host modes. 0 (B_0x0): Normal mode 1 (B_0x1): Force host mode |
| FDMOD | Force device mode Writing a 1 to this bit, forces the core to device mode irrespective of the OTG_ID input pin. After setting the force bit, the application must wait at least 25 ms before the change takes effect. Note: Accessible in both device and host modes. 0 (B_0x0): Normal mode 1 (B_0x1): Force device mode |