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stm32 /stm32h7rs /STM32H7S /OTG_HS /OTG_HFIR

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Interpret as OTG_HFIR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0FRIVL0 (B_0x0)RLDCTRL

RLDCTRL=B_0x0

Description

OTG host frame interval register

Fields

FRIVL

Frame interval
RLDCTRL

Reload control This bit allows dynamic reloading of the HFIR register during run time. This bit needs to be programmed during initial configuration and its value must not be changed during run time. RLDCTRL = 0 is not recommended.

0 (B_0x0): The HFIR cannot be reloaded dynamically

1 (B_0x1): The HFIR can be dynamically reloaded during run time.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32