OTG power and clock gating control register
| STPPCLK | Stop PHY clock The application sets this bit to stop the PHY clock when the USB is suspended, the session is not valid, or the device is disconnected. The application clears this bit when the USB is resumed or a new session starts. |
| GATEHCLK | Gate HCLK The application sets this bit to gate HCLK to modules other than the AHB Slave and Master and wakeup logic when the USB is suspended or the session is not valid. The application clears this bit when the USB is resumed or a new session starts. |
| PHYSUSP | PHY suspended Indicates that the PHY has been suspended. This bit is updated once the PHY is suspended after the application has set the STPPCLK bit. |
| ENL1GTG | Enable sleep clock gating When this bit is set, core internal clock gating is enabled in Sleep state if the core cannot assert utmi_l1_suspend_n. When this bit is not set, the PHY clock is not gated in Sleep state. |
| PHYSLEEP | PHY in Sleep This bit indicates that the PHY is in the Sleep state. |
| SUSP | Deep Sleep This bit indicates that the PHY is in Deep Sleep when in L1 state. |