CNTGATECLK=B_0x0
OTG power and clock gating control register 1
| GATEEN | Enable active clock gating The application programs GATEEN to enable Active Clock Gating feature for the PHY and AHB clocks. |
| CNTGATECLK | Counter for clock gating Indicates to the controller how many PHY Clock cycles and AHB Clock cycles of ‘IDLE’ (no activity) the controller waits for before Gating the respective PHY and AHB clocks internal to the controller. 0 (B_0x0): 64 clocks 1 (B_0x1): 128 clocks 2 (B_0x2): FIELD Reserved 3 (B_0x3): FIELD Reserved |
| RAMGATEEN | Enable RAM clock gating Enable gating of the FIFO RAM. |