BUSY=B_0x0, INITOK=B_0x0, RAMERRF=B_0x0, ADDRERRF=B_0x0, OPERRF=B_0x0, PROCENDF=B_0x0, LMF=B_0x0
PKA status register
| INITOK | PKA initialization OK This bit is asserted when PKA initialization is complete. When RNG is not able to output proper random numbers INITOK stays at 0. 0 (B_0x0): PKA is not initialized correctly. START bit cannot be set. 1 (B_0x1): PKA is initialized correctly and can be used normally. |
| LMF | Limited mode flag This bit is updated when EN bit in PKA_CR is set 0 (B_0x0): All values documented in MODE bitfield can be used. 1 (B_0x1): Only ECDSA verification (MODE = 0x26) is supported by the PKA. |
| BUSY | PKA operation is in progress This bit is set to 1 whenever START bit in the PKA_CR is set. It is automatically cleared when the computation is complete, meaning that PKA RAM can be safely accessed and a new operation can be started. If PKA is started with a wrong opcode, it is busy for a couple of cycles, then it aborts automatically the operation and go back to ready (BUSY bit is set to 0). 0 (B_0x0): No operation is in progress (default) 1 (B_0x1): An operation is in progress |
| PROCENDF | PKA End of Operation flag 0 (B_0x0): Operation in progress 1 (B_0x1): PKA operation is completed. This flag is set when the BUSY bit is deasserted. |
| RAMERRF | PKA RAM error flag This bit is cleared using RAMERRFC bit in PKA_CLRFR. 0 (B_0x0): No PKA RAM access error 1 (B_0x1): An AHB access to the PKA RAM occurred while the PKA core was computing and using its internal RAM (AHB PKA_RAM access are not allowed while PKA operation is in progress). |
| ADDRERRF | Address error flag This bit is cleared using ADDRERRFC bit in PKA_CLRFR. 0 (B_0x0): No address error 1 (B_0x1): Address access is out of range (unmapped address) |
| OPERRF | Operation error flag This bit is cleared using OPERRFC bit in PKA_CLRFR. 0 (B_0x0): No event error 1 (B_0x1): An illegal or unknown operation has been selected in PKA_CR register |