DMAEN=B_0x0, EDM=B_0x0, DEPOL=B_0x0, DERDYCFG=B_0x0, RDYPOL=B_0x0, CKSRC=B_0x0, ENABLE=B_0x0, CKPOL=B_0x0, OUTEN=B_0x0
PSSI control register
| CKPOL | Parallel data clock polarity This bit configures the capture edge of the parallel clock or the edge used for driving outputs, depending on OUTEN. 0 (B_0x0): Falling edge active for inputs or rising edge active for outputs 1 (B_0x1): Rising edge active for inputs or falling edge active for outputs. |
| DEPOL | Data enable (PSSI_DE) polarity This bit indicates the level on the PSSI_DE pin when the data are not valid on the parallel interface. 0 (B_0x0): PSSI_DE active low (0 indicates that data is valid) 1 (B_0x1): PSSI_DE active high (1 indicates that data is valid) |
| RDYPOL | Ready (PSSI_RDY) polarity This bit indicates the level on the PSSI_RDY pin when the data are not valid on the parallel interface. 0 (B_0x0): PSSI_RDY active low (0 indicates that the receiver is ready to receive) 1 (B_0x1): PSSI_RDY active high (1 indicates that the receiver is ready to receive) |
| EDM | Extended data mode 0 (B_0x0): Interface captures 8-bit data on every parallel data clock 1 (B_0x1): Reserved, must not be selected 2 (B_0x2): Reserved, must not be selected 3 (B_0x3): The interface captures 16-bit data on every parallel data clock |
| ENABLE | PSSI enable The contents of the FIFO are flushed when ENABLE is cleared to 0. Note: When ENABLE=1, the content of PSSI_CR must not be changed, except for the ENABLE bit itself. All configuration bits can change as soon as ENABLE changes from 0 to 1. Note: The DMA controller and all PSSI configuration registers must be programmed correctly before setting the ENABLE bit to 1. 0 (B_0x0): PSSI disabled 1 (B_0x1): PSSI enabled |
| DERDYCFG | Data enable and ready configuration When the PSSI_RDY function is mapped to the PSSI_DE pin (settings 101 or 111), it is still the RDYPOL bit which determines its polarity. Similarly, when the PSSI_DE function is mapped to the PSSI_RDY pin (settings 110 or 111), it is still the DEPOL bit which determines its polarity. 0 (B_0x0): PSSI_DE and PSSI_RDY both disabled 1 (B_0x1): Only PSSI_RDY enabled 2 (B_0x2): Only PSSI_DE enabled 3 (B_0x3): Both PSSI_RDY and PSSI_DE alternate functions enabled 4 (B_0x4): Both PSSI_RDY and PSSI_DE features enabled - bidirectional on PSSI_RDY pin (see Bidirectional PSSI_DE/PSSI_RDY signal on page 2965) 5 (B_0x5): Only PSSI_RDY function enabled, but mapped to PSSI_DE pin 6 (B_0x6): Only PSSI_DE function enabled, but mapped to PSSI_RDY pin 7 (B_0x7): Both PSSI_RDY and PSSI_DE features enabled - bidirectional on PSSI_DE pin (see Bidirectional PSSI_DE/PSSI_RDY signal on page 2965) |
| CKSRC | Clock source This bit configures the clock source of the PSSI_PDCK. 0 (B_0x0): External clock (PSSI_PDCK in input) 1 (B_0x1): Internal clock (PSSI_PDCK in output) |
| DMAEN | DMA enable bit 0 (B_0x0): DMA transfers are disabled. The user application can directly access the PSSI_DR register when DMA transfers are disabled. 1 (B_0x1): DMA transfers are enabled (default configuration). A DMA channel in the general-purpose DMA controller must be configured to perform transfers from/to PSSI_DR. |
| OUTEN | Data direction selection bit 0 (B_0x0): Receive mode: data is input synchronously with PSSI_PDCK 1 (B_0x1): Transmit mode: data is output synchronously with PSSI_PDCK |