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stm32 /stm32h7rs /STM32H7S /PSSI /PSSI_MIS

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Interpret as PSSI_MIS

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)OVR_MIS

OVR_MIS=B_0x0

Description

PSSI masked interrupt status register

Fields

OVR_MIS

Data buffer overrun/underrun masked interrupt status This bit is set to 1 only when PSSI_IER/OVR_IE and PSSI_RIS/OVR_RIS are both set to 1.

0 (B_0x0): No interrupt is generated when an overrun/underrun error occurs

1 (B_0x1): An interrupt is generated if there is either an overrun or an underrun error and the OVR_IE bit is set in PSSI_IER.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32