GECCDEBWIE=B_0x0, GECCDEIE=B_0x0, GIE=B_0x0, GECCSEIE=B_0x0
RAMECC interrupt enable register
| GIE | Global interrupt enable When GIE bit is set to 1, an interrupt is generated when an enabled global ECC error (GECCDEBWIE, GECCDEIE or GECCSEIE) occurs. 0 (B_0x0): no interrupt generated when an ECC error occurs 1 (B_0x1): interrupt generated when an ECC error occurs |
| GECCSEIE | Global ECC single error interrupt enable When GECCSEIE bit is set to 1, an interrupt is generated when an ECC single error occurs during a read operation from RAM. 0 (B_0x0): no interrupt generated when an ECC single error occurs 1 (B_0x1): interrupt generated when an ECC single error occurs |
| GECCDEIE | Global ECC double error interrupt enable When GECCDEIE bit is set to 1, an interrupt is generated when an ECC double detection error occurs during a read operation from RAM. 0 (B_0x0): no interrupt generated when an ECC double detection error occurs 1 (B_0x1): interrupt generated if an ECC double detection error occurs |
| GECCDEBWIE | Global ECC double error on byte write (BW) interrupt enable When GECCDEBWIE bit is set to 1, an interrupt is generated when an ECC double detection error occurs during a byte write operation to RAM (incomplete word write). 0 (B_0x0): no interrupt generated when an ECC double detection error occurs on byte write 1 (B_0x1): interrupt generated if an ECC double detection error occurs on byte write |