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stm32 /stm32h7rs /STM32H7S /RAMCFG /RAMECC_M3SR

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Interpret as RAMECC_M3SR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)SEDCF 0 (B_0x0)DEDF 0 (B_0x0)DEBWDF

SEDCF=B_0x0, DEDF=B_0x0, DEBWDF=B_0x0

Description

RAMECC monitor 3 status register

Fields

SEDCF

ECC single error detected and corrected flag This bit is set by hardware. It is cleared by software by writing a 0

0 (B_0x0): no error detected and corrected

1 (B_0x1): error detected and corrected
DEDF

ECC double error detected flag This bit is set by hardware. It is cleared by software by writing a 0

0 (B_0x0): no error detected

1 (B_0x1): error detected
DEBWDF

ECC double error on byte write (BW) detected flag This bit is set by hardware. It is cleared by software by writing a 0

0 (B_0x0): no error detected

1 (B_0x1): error detected

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32