ECCDEIE=B_0x0, ECCDECEN=B_0x0, ECCDEBWCEN=B_0x0, ECCELEN=B_0x0, ECCSEIE=B_0x0, ECCTEA=B_0x0, ECCSECEN=B_0x0, ECCDEBWIE=B_0x0
RAMECC monitor 5 configuration register
| ECCSEIE | ECC single error interrupt enable When ECCSEIE bit is set to 1, monitor x generates an interrupt when an ECC single error occurs during a read operation from RAM. 0 (B_0x0): no interrupt generated when an ECC single error occurs 1 (B_0x1): interrupt generated when an ECC single error occurs |
| ECCDEIE | ECC double error interrupt enable When ECCDEIE bit is set to 1, monitor x generates an interrupt when an ECC double detection error occurs during a read operation from RAM. 0 (B_0x0): no interrupt generated when an ECC double detection error occurs 1 (B_0x1): interrupt generated if an ECC double detection error occurs |
| ECCDEBWIE | ECC double error on byte write (BW) interrupt enable When ECCDEBWIE bit is set to 1, monitor x generates an interrupt when an ECC double detection error occurs during a byte write operation to RAM. 0 (B_0x0): no interrupt generated when an ECC double detection error occurs on byte write 1 (B_0x1): interrupt generated if an ECC double detection error occurs on byte write |
| ECCELEN | ECC error latching enable When ECCELEN bit is set to 1, if an ECC error occurs (both for single error correction or double detection) during a read operation, the context (address, data and ECC code) that generated the error are latched to their respective registers. 0 (B_0x0): no error context preserved when an ECC error occurs 1 (B_0x1): error context preserved when an ECC error occurs |
| ECCSECEN | ECC single error counter enable When ECCSECEN bit is set to 1, the occurrence counter is incremented when an ECC single error occurs during a read operation from RAM. 0 (B_0x0): no counter increment when an ECC single error occurs 1 (B_0x1): counter increment when an ECC single error occurs |
| ECCDECEN | ECC double error counter enable When ECCDECEN bit is set to 1, the occurrence counter is incremented when an ECC double detection error occurs during a read operation from RAM. 0 (B_0x0): no counter increment when an ECC double detection error occurs 1 (B_0x1): counter increment when an ECC double detection error occurs |
| ECCDEBWCEN | ECC double error on byte write (BW) counter enable When ECCDEBWCEN bit is set to 1, the occurrence counter is incremented when an ECC double detection error occurs during a byte write operation to RAM. 0 (B_0x0): no counter increment when an ECC double detection error occurs on byte write 1 (B_0x1): counter increment when an ECC double detection error occurs on byte write |
| ECCTEA | ECC Test ECC access 0 (B_0x0): inactive 1 (B_0x1): write and read access blocked on data memory 2 (B_0x2): write and read access blocked on ECC memory 3 (B_0x3): inactive |