SRAM2LPEN=B_0x0, PSSILPEN=B_0x0, SDMMC2LPEN=B_0x0, SRAM1LPEN=B_0x0, CORDICLPEN=B_0x0
RCC AHB2 low-power clock enable register
| PSSILPEN | PSSI peripheral clock enable in low-power mode Set and reset by software. 0 (B_0x0): PSSI peripheral clock disabled in low-power mode 1 (B_0x1): PSSI peripheral clock enabled in low-power mode (default after reset) |
| SDMMC2LPEN | SDMMC2 and SDMMC2 delay clock enable in low-power mode Set and reset by software. 0 (B_0x0): SDMMC2 and SDMMC2 delay clock disabled in low-power mode 1 (B_0x1): SDMMC2 and SDMMC2 delay clock enabled in low-power mode (default after reset) |
| CORDICLPEN | CORDIC clock enable in low-power mode Set and reset by software. 0 (B_0x0): CORDIC clock disabled in low-power mode 1 (B_0x1): CORDIC clock enabled in low-power mode (default after reset) |
| SRAM1LPEN | SRAM1 clock enable in low-power mode Set and reset by software. 0 (B_0x0): SRAM1 clock disabled in low-power mode 1 (B_0x1): SRAM1 clock enabled in low-power mode (default after reset) |
| SRAM2LPEN | SRAM2 clock enable in low-power mode Set and reset by software. 0 (B_0x0): SRAM2 clock disabled in low-power mode 1 (B_0x1): SRAM2 clock enabled in low-power mode (default after reset) |