XSPIMLPEN=B_0x0, GPULPEN=B_0x0, JPEGLPEN=B_0x0, GFXMMULPEN=B_0x0, XSPI1LPEN=B_0x0, AXISRAMLPEN=B_0x0, DMA2DLPEN=B_0x0, HPDMA1LPEN=B_0x0, DTCM1LPEN=B_0x0, ITCMLPEN=B_0x0, FMCLPEN=B_0x0, DTCM2LPEN=B_0x0, FLITFLPEN=B_0x0, XSPI2LPEN=B_0x0, SDMMC1LPEN=B_0x0
RCC AHB5 low-power clock enable register
| HPDMA1LPEN | HPDMA1 low-power peripheral clock enable Set and reset by software. 0 (B_0x0): HPDMA1 peripheral clock disabled during Sleep mode 1 (B_0x1): HPDMA1 peripheral clock enabled during Sleep mode (default after reset) |
| DMA2DLPEN | DMA2D low-power peripheral clock enable Set and reset by software. 0 (B_0x0): DMA2D peripheral clock disabled during Sleep mode 1 (B_0x1): DMA2D peripheral clock enabled during Sleep mode (default after reset) |
| FLITFLPEN | FLITF low-power peripheral clock enable Set and reset by software. 0 (B_0x0): FLITF peripheral clock disabled during Sleep mode 1 (B_0x1): FLITF peripheral clock enabled during Sleep mode (default after reset) |
| JPEGLPEN | JPEG clock enable during Sleep mode Set and reset by software. 0 (B_0x0): JPEG peripheral clock disabled during Sleep mode 1 (B_0x1): JPEG peripheral clock enabled during Sleep mode (default after reset) |
| FMCLPEN | FMC and MCE3 peripheral clocks enable during Sleep mode Set and reset by software. The hardware prevents writing this bit if FMCCKP = 1. The peripheral clocks of the FMC are the kernel clock selected by FMCSEL, and the hclk5 bus interface clock. 0 (B_0x0): FMC and MCE3 peripheral clocks disabled during Sleep mode 1 (B_0x1): FMC and MCE3 peripheral clocks enabled during Sleep mode (default after reset): |
| XSPI1LPEN | XSPI1 and MCE1 low-power peripheral clock enable Set and reset by software. The hardware prevents writing this bit if XSPICKP = 1. 0 (B_0x0): XSPI1 and MCE1 peripheral clock disabled during Sleep mode 1 (B_0x1): XSPI1 and MCE1 peripheral clock enabled during Sleep mode (default after reset) |
| SDMMC1LPEN | SDMMC1 and SDMMC1 delay low-power peripheral clock enable Set and reset by software. 0 (B_0x0): SDMMC1 and SDMMC1 delay peripheral clock disabled during Sleep mode 1 (B_0x1): SDMMC1 and SDMMC1 delay peripheral clock enabled during Sleep mode (default after reset) |
| XSPI2LPEN | XSPI2 and MCE2 low-power peripheral clock enable Set and reset by software. The hardware prevents writing this bit if XSPICKP = 1. 0 (B_0x0): XSPI2 and MCE2 peripheral clock disabled during Sleep mode 1 (B_0x1): XSPI2 and MCE2 peripheral clock enabled during Sleep mode (default after reset) |
| XSPIMLPEN | XSPIM low-power peripheral clock enable Set and reset by software. 0 (B_0x0): XSPIM interface peripheral clock disabled during Sleep mode 1 (B_0x1): XSPIM interface peripheral clock enabled during Sleep mode (default after reset) |
| GFXMMULPEN | GFXMMU low-power peripheral clock enable Set and reset by software. 0 (B_0x0): GFXMMU interface peripheral clock disabled during Sleep mode 1 (B_0x1): GFXMMU interface peripheral clock enabled during Sleep mode (default after reset) |
| GPULPEN | GPU low-power peripheral clock enable Set and reset by software. 0 (B_0x0): GPU interface clock peripheral disabled during Sleep mode 1 (B_0x1): GPU interface clock peripheral enabled during Sleep mode (default after reset) |
| DTCM1LPEN | DTCM1 low-power peripheral clock enable Set and reset by software. 0 (B_0x0): DTCM1 interface peripheral clock disabled during Sleep mode 1 (B_0x1): DTCM1 interface peripheral clock enabled during Sleep mode (default after reset) |
| DTCM2LPEN | DTCM2 low-power peripheral clock enable Set and reset by software. 0 (B_0x0): DTCM2 interface peripheral clock disabled during Sleep mode 1 (B_0x1): DTCM2 interface peripheral clock enabled during Sleep mode (default after reset) |
| ITCMLPEN | ITCM low-power peripheral clock enable Set and reset by software. 0 (B_0x0): ITCM interface peripheral clock disabled during Sleep mode 1 (B_0x1): ITCM interface peripheral clock enabled during Sleep mode (default after reset) |
| AXISRAMLPEN | AXISRAM[4:1] low-power peripheral clock enable Set and reset by software. 0 (B_0x0): AXISRAM[4:1] interface peripheral clock disabled during Sleep mode 1 (B_0x1): AXISRAM[4:1] interface peripheral clock enabled during Sleep mode (default after reset) |