MDIOSLPEN=B_0x0, UCPDLPEN=B_0x0, FDCANLPEN=B_0x0, CRSLPEN=B_0x0
RCC APB1 low-power clock enable register 2
| CRSLPEN | clock recovery system peripheral clock enable in low-power mode Set and reset by software. 0 (B_0x0): CRS peripheral clock disabled in low-power mode 1 (B_0x1): CRS peripheral clock enabled in low-power mode (default after reset) |
| MDIOSLPEN | MDIOS peripheral clock enable in low-power mode Set and reset by software. 0 (B_0x0): MDIOS peripheral clock disabled in low-power mode 1 (B_0x1): MDIOS peripheral clock enabled in low-power mode (default after reset) |
| FDCANLPEN | FDCAN peripheral clock enable in low-power mode Set and reset by software. 0 (B_0x0): FDCAN peripheral clock disabled in low-power mode 1 (B_0x1): FDCAN peripheral clock enabled in low-power mode (default after reset) |
| UCPDLPEN | UCPD peripheral clock enable in low-power mode Set and reset by software. 0 (B_0x0): UCPD peripheral clock disabled in low-power mode 1 (B_0x1): UCPD peripheral clock enabled in low-power mode (default after reset) |