Regviz

stm32 /stm32h7rs /STM32H7S /RCC /RCC_APB1RSTR2

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as RCC_APB1RSTR2

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32h7rs/STM32H7R/RCC/RCC_APB1RSTR2#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)CRSRST 0 (B_0x0)MDIOSRST 0 (B_0x0)FDCANRST 0 (B_0x0)UCPDRST

CRSRST=B_0x0, MDIOSRST=B_0x0, UCPDRST=B_0x0, FDCANRST=B_0x0

Description

RCC APB1 peripheral reset register 2

Fields

CRSRST

clock recovery system reset Set and reset by software.

0 (B_0x0): does not reset CRS (default after reset)

1 (B_0x1): resets CRS
MDIOSRST

MDIOS block reset Set and reset by software.

0 (B_0x0): does not reset the MDIOS block (default after reset)

1 (B_0x1): resets the MDIOS block
FDCANRST

FDCAN block reset Set and reset by software.

0 (B_0x0): does not reset the FDCAN block (default after reset)

1 (B_0x1): resets the FDCAN block
UCPDRST

UCPD block reset Set and reset by software.

0 (B_0x0): does not reset the UCPD block (default after reset)

1 (B_0x1): resets the UCPD block

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32