SPI1SEL=B_0x0, SAI2SEL=B_0x0, USART1SEL=B_0x0, SAI1SEL=B_0x0, SPI45SEL=B_0x0
RCC APB2 peripherals kernel clock selection register
| USART1SEL | USART1 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled 0 (B_0x0): pclk2 selected as kernel clock (default after reset) 1 (B_0x1): pll2_q_ck selected as kernel clock 2 (B_0x2): pll3_q_ck selected as kernel clock 3 (B_0x3): hsi_ker_ck selected as kernel clock 4 (B_0x4): csi_ker_ck selected as kernel clock 5 (B_0x5): lse_ck selected as kernel clock |
| SPI45SEL | SPI4 and 5 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled 0 (B_0x0): pclk2 selected as kernel clock (default after reset) 1 (B_0x1): pll2_q_ck is selected as kernel clock 2 (B_0x2): pll3_q_ck is selected as kernel clock 3 (B_0x3): hsi_ker_ck is selected as kernel clock 4 (B_0x4): csi_ker_ck is selected as kernel clock 5 (B_0x5): hse_ker_ck is selected as kernel clock |
| SPI1SEL | SPI/I2S1 kernel clock source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not be possible to switch to another clock. Refer to Clock switches and gating on page 437 for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin. 0 (B_0x0): pll1_q_ck selected as SPI/I2S1 and 7 kernel clock (default after reset) 1 (B_0x1): pll2_p_ck selected as SPI/I2S1 and 7 kernel clock 2 (B_0x2): pll3_p_ck selected as SPI/I2S1 and 7 kernel clock 3 (B_0x3): I2S_CKIN selected as SPI/I2S1 and 7 kernel clock 4 (B_0x4): per_ck selected as SPI/I2S1,and 7 kernel clock |
| SAI1SEL | SAI1 kernel clock source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not possible to switch to another clock. Refer to Clock switches and gating on page 437 for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin. 0 (B_0x0): pll1_q_ck selected as SAI1 kernel clock (default after reset) 1 (B_0x1): pll2_p_ck selected as SAI1 kernel clock 2 (B_0x2): pll3_p_ck selected as SAI1 kernel clock 3 (B_0x3): I2S_CKIN selected as SAI1 kernel clock 4 (B_0x4): per_ck selected as SAI1 kernel clock |
| SAI2SEL | SAI2 kernel clock source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not possible to switch to another clock. Refer to Clock switches and gating on page 437 for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin. spdifrx_symb_ck is the symbol clock generated by the spdifrx (see Figure 51). 0 (B_0x0): pll1_q_ck selected as SAI2 kernel clock (default after reset) 1 (B_0x1): pll2_p_ck selected as SAI2 kernel clock 2 (B_0x2): pll3_p_ck selected as SAI2 kernel clock 3 (B_0x3): I2S_CKIN selected as SAI2 kernel clock 4 (B_0x4): per_ck selected as SAI2 kernel clock 5 (B_0x5): spdifrx_symb_ck selected as SAI2 kernel clock |