LPUART1EN=B_0x0, LPTIM2EN=B_0x0, LPTIM5EN=B_0x0, LPTIM3EN=B_0x0, VREFEN=B_0x0, TMPSENSEN=B_0x0, SPI6EN=B_0x0, SBSEN=B_0x0, LPTIM4EN=B_0x0, RTCAPBEN=B_0x0
RCC APB4 clock enable register
| SBSEN | SBS peripheral clock enable Set and reset by software. 0 (B_0x0): SBS peripheral clock disabled (default after reset) 1 (B_0x1): SBS peripheral clock enabled |
| LPUART1EN | LPUART1 peripheral clocks enable Set and reset by software. The peripheral clocks of the LPUART1 are the kernel clock selected by LPUART1SEL and provided to UCLK input, and the pclk4 bus interface clock. 0 (B_0x0): LPUART1 peripheral clocks disabled (default after reset) 1 (B_0x1): LPUART1 peripheral clocks enabled |
| SPI6EN | SPI/I2S6 peripheral clocks enable Set and reset by software. The peripheral clocks of the SPI/I2S6 are the kernel clock selected by SPI6SEL and provided to com_clk input, and the pclk4 bus interface clock. 0 (B_0x0): SPI/I2S6 peripheral clocks disabled (default after reset) 1 (B_0x1): SPI/I2S6 peripheral clocks enabled |
| LPTIM2EN | LPTIM2 peripheral clocks enable Set and reset by software. The LPTIM2 kernel clock can be selected by LPTIM23SEL. 0 (B_0x0): LPTIM2 peripheral clocks disabled (default after reset) 1 (B_0x1): LPTIM2 peripheral clocks enabled |
| LPTIM3EN | LPTIM3 peripheral clocks enable Set and reset by software. The LPTIM3 kernel clock can be selected by LPTIM23SEL. 0 (B_0x0): LPTIM3 peripheral clocks disabled (default after reset) 1 (B_0x1): LPTIM3 peripheral clocks enabled |
| LPTIM4EN | LPTIM4 peripheral clocks enable Set and reset by software. The LPTIM4 kernel clock can be selected by LPTIM45SEL. 0 (B_0x0): LPTIM4 peripheral clocks disabled (default after reset) 1 (B_0x1): LPTIM4 peripheral clocks enabled |
| LPTIM5EN | LPTIM5 peripheral clocks enable Set and reset by software. The LPTIM5 kernel clock can be selected by LPTIM45SEL. 0 (B_0x0): LPTIM5 peripheral clocks disabled (default after reset) 1 (B_0x1): LPTIM5 peripheral clocks enabled |
| VREFEN | VREF peripheral clock enable Set and reset by software. 0 (B_0x0): VREF peripheral clock disabled (default after reset) 1 (B_0x1): VREF peripheral clock enabled |
| RTCAPBEN | RTC APB clock enable Set and reset by software. 0 (B_0x0): The register clock interface of the RTC (APB) is disabled 1 (B_0x1): The register clock interface of the RTC (APB) is enabled (default after reset) |
| TMPSENSEN | Temperature Sensor peripheral clock enable Set and reset by software. 0 (B_0x0): TMPSENS peripheral clock disabled (default after reset) 1 (B_0x1): TMPSENS peripheral clock enabled |