GFXTIMEN=B_0x0, DCMIPPEN=B_0x0, LTDCEN=B_0x0
RCC APB5 clock enable register
| LTDCEN | LTDC peripheral clock enable Provides the pixel clock (ltdc_clk) to the LTDC block. Set and reset by software. 0 (B_0x0): LTDC peripheral clock disabled (default after reset) 1 (B_0x1): LTDC peripheral clock provided to the LTDC block |
| DCMIPPEN | DCMIPP peripheral clock enable Set and reset by software. 0 (B_0x0): DCMIPP peripheral clock disabled (default after reset) 1 (B_0x1): DCMIPP peripheral clock provided |
| GFXTIMEN | GFXTIM peripheral clock enable Set and reset by software. 0 (B_0x0): GFXTIM peripheral clock disabled (default after reset) 1 (B_0x1): GFXTIM peripheral clock provided |