stm32 /stm32h7rs /STM32H7S /RCC /RCC_APB5LPENR

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Interpret as RCC_APB5LPENR

LTDCLPEN=B_0x0, DCMIPPLPEN=B_0x0, GFXTIMLPEN=B_0x0

Description

RCC APB5 sleep clock register

Fields

LTDCLPEN	LTDC peripheral clock enable in low-power mode Set and reset by software. 0 (B_0x0): LTDC peripheral clock disabled in low-power mode 1 (B_0x1): LTDC peripheral clock enabled in low-power mode (default after reset)
DCMIPPLPEN	DCMIPP peripheral clock enable in low-power mode Set and reset by software. 0 (B_0x0): DCMIPP peripheral clock disabled in low-power mode 1 (B_0x1): DCMIPP peripheral clock enabled in low-power mode (default after reset)
GFXTIMLPEN	GFXTIM peripheral clock enable in low-power mode Set and reset by software. 0 (B_0x0): GFXTIM peripheral clock disabled in low-power mode 1 (B_0x1): GFXTIM peripheral clock enabled in low-power mode (default after reset)

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