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stm32 /stm32h7rs /STM32H7S /RCC /RCC_APB5RSTR

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Interpret as RCC_APB5RSTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)LTDCRST 0 (B_0x0)DCMIPPRST 0 (B_0x0)GFXTIMRST

LTDCRST=B_0x0, GFXTIMRST=B_0x0, DCMIPPRST=B_0x0

Description

RCC APB5 peripheral reset register

Fields

LTDCRST

LTDC block reset Set and reset by software.

0 (B_0x0): does not reset the LTDC block (default after reset)

1 (B_0x1): resets the LTDC block
DCMIPPRST

DCMIPP block reset Set and reset by software.

0 (B_0x0): does not reset the DCMIPP block (default after reset)

1 (B_0x1): resets the DCMIPP block
GFXTIMRST

GFXTIM block reset Set and reset by software.

0 (B_0x0): does not reset the GFXTIM block (default after reset)

1 (B_0x1): resets the GFXTIM block

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32