RCC APB clocks configuration register
| PPRE1 | CPU domain APB1 prescaler Set and reset by software to control the division factor of rcc_pclk1. The clock is divided by the new prescaler factor from 1 to 16 cycles of sys_bus_ck after PPRE1 write. 0xx: rcc_pclk1 = sys_bus_ck (default after reset) 4 (B_0x4): rcc_pclk1 = sys_bus_ck / 2 5 (B_0x5): rcc_pclk1 = sys_bus_ck / 4 6 (B_0x6): rcc_pclk1 = sys_bus_ck / 8 7 (B_0x7): rcc_pclk1 = sys_bus_ck / 16 |
| PPRE2 | CPU domain APB2 prescaler Set and reset by software to control the division factor of rcc_pclk2. The clock is divided by the new prescaler factor from 1 to 16 cycles of sys_bus_ck after PPRE2 write. 0xx: rcc_pclk2 = sys_bus_ck (default after reset) 4 (B_0x4): rcc_pclk2 = sys_bus_ck / 2 5 (B_0x5): rcc_pclk2 = sys_bus_ck / 4 6 (B_0x6): rcc_pclk2 = sys_bus_ck / 8 7 (B_0x7): rcc_pclk2 = sys_bus_ck / 16 |
| PPRE4 | CPU domain APB4 prescaler Set and reset by software to control the division factor of rcc_pclk4. The clock is divided by the new prescaler factor from 1 to 16 cycles of sys_bus_ck after PPRE4 write. 0xx: rcc_pclk4 = sys_bus_ck (default after reset) 4 (B_0x4): rcc_pclk4 = sys_bus_ck / 2 5 (B_0x5): rcc_pclk4 = sys_bus_ck / 4 6 (B_0x6): rcc_pclk4 = sys_bus_ck / 8 7 (B_0x7): rcc_pclk4 = sys_bus_ck / 16 |
| PPRE5 | CPU domain APB5 prescaler Set and reset by software to control the division factor of rcc_pclk5. The clock is divided by the new prescaler factor from 1 to 16 cycles of sys_bus_ck after PPRE5 write. 0xx: rcc_pclk5 = sys_bus_ck (default after reset) 4 (B_0x4): rcc_pclk5 = sys_bus_ck / 2 5 (B_0x5): rcc_pclk5 = sys_bus_ck / 4 6 (B_0x6): rcc_pclk5 = sys_bus_ck / 8 7 (B_0x7): rcc_pclk5 = sys_bus_ck / 16 |