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stm32 /stm32h7rs /STM32H7S /RCC /RCC_CICR

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Interpret as RCC_CICR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)LSIRDYC 0 (B_0x0)LSERDYC 0 (B_0x0)HSIRDYC 0 (B_0x0)HSERDYC 0 (B_0x0)CSIRDYC 0 (B_0x0)HSI48RDYC 0 (B_0x0)PLL1RDYC 0 (B_0x0)PLL2RDYC 0 (B_0x0)PLL3RDYC 0 (B_0x0)LSECSSC 0 (B_0x0)HSECSSC

HSECSSC=B_0x0, LSECSSC=B_0x0, LSIRDYC=B_0x0, HSERDYC=B_0x0, HSI48RDYC=B_0x0, PLL2RDYC=B_0x0, HSIRDYC=B_0x0, LSERDYC=B_0x0, PLL3RDYC=B_0x0, PLL1RDYC=B_0x0, CSIRDYC=B_0x0

Description

RCC clock source interrupt clear register

Fields

LSIRDYC

LSI ready interrupt clear Set by software to clear LSIRDYF. Reset by hardware when clear done.

0 (B_0x0): LSIRDYF no effect (default after reset)

1 (B_0x1): LSIRDYF cleared
LSERDYC

LSE ready interrupt clear Set by software to clear LSERDYF. Reset by hardware when clear done.

0 (B_0x0): LSERDYF no effect (default after reset)

1 (B_0x1): LSERDYF cleared
HSIRDYC

HSI ready interrupt clear Set by software to clear HSIRDYF. Reset by hardware when clear done.

0 (B_0x0): HSIRDYF no effect (default after reset)

1 (B_0x1): HSIRDYF cleared
HSERDYC

HSE ready interrupt clear Set by software to clear HSERDYF. Reset by hardware when clear done.

0 (B_0x0): HSERDYF no effect (default after reset)

1 (B_0x1): HSERDYF cleared
CSIRDYC

CSI ready interrupt clear Set by software to clear CSIRDYF. Reset by hardware when clear done.

0 (B_0x0): CSIRDYF no effect (default after reset)

1 (B_0x1): CSIRDYF cleared
HSI48RDYC

HSI48 ready interrupt clear Set by software to clear HSI48RDYF. Reset by hardware when clear done.

0 (B_0x0): HSI48RDYF no effect (default after reset)

1 (B_0x1): HSI48RDYF cleared
PLL1RDYC

PLL1 ready interrupt clear Set by software to clear PLL1RDYF. Reset by hardware when clear done.

0 (B_0x0): PLL1RDYF no effect (default after reset)

1 (B_0x1): PLL1RDYF cleared
PLL2RDYC

PLL2 ready interrupt clear Set by software to clear PLL2RDYF. Reset by hardware when clear done.

0 (B_0x0): PLL2RDYF no effect (default after reset)

1 (B_0x1): PLL2RDYF cleared
PLL3RDYC

PLL3 ready interrupt clear Set by software to clear PLL3RDYF. Reset by hardware when clear done.

0 (B_0x0): PLL3RDYF no effect (default after reset)

1 (B_0x1): PLL3RDYF cleared
LSECSSC

LSE clock security system interrupt clear Set by software to clear LSECSSF. Reset by hardware when clear done.

0 (B_0x0): LSECSSF no effect (default after reset)

1 (B_0x1): LSECSSF cleared
HSECSSC

HSE clock security system interrupt clear Set by software to clear HSECSSF. Reset by hardware when clear done.

0 (B_0x0): HSECSSF no effect (default after reset)

1 (B_0x1): HSECSSF cleared

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32